Hello, I'm
Deekshith.

Developed a cycle-accurate simulator for an out-of-order (OOO) superscalar processor to model dynamic instruction scheduling.

• Implemented core microarchitectural components essential for OOO execution, including a Reorder Buffer (ROB), a unified Issue Queue (IQ), and a Rename Map Table (RMT).
• Modeled the complete multi-stage pipeline (Fetch, Decode, Rename, Register Read, Dispatch, Issue, Execute, Writeback, and Retire) to resolve true data dependencies and structural hazards.
• Analyzed processor performance by processing instruction trace files to generate detailed cycle-by-cycle timing reports and calculate final metrics like Instructions Per Cycle (IPC).

Aug 2019 - Jul 2025 (Includes Internship & Full-time)

• Developed and optimized firmware for the Flight Warning Computer (A320 aircraft) using C/C++ and RTOS, demonstrating deep understanding of hardware-software integration and embedded system performance.
• Conducted requirement-based testing and real-time hardware debugging using Lauterbach Trace32 and GDB, mirroring post-silicon validation and hardware bring-up processes.
• Collaborated with cross-functional hardware and verification teams to ensure real-time system reliability and SoC-level data communication consistency.
• Engineered and maintained CI/CD pipelines in Jenkins, improving build and deployment efficiency by 50% through automated testing and system-level integration.

Designed to model speculative data access and analyze performance metrics.

• Developed a configurable simulator for multi-level cache hierarchies (L1, L2).
• Implemented a stream buffer prefetching unit to model speculative data access.
• Evaluated system-level trade-offs in latency, bandwidth, and energy using CACTI models.

Designed a machine learning model to perform automatic modulation classification (AMC).

• Developed and trained a deep neural network (DNN) to predict modulation schemes.
• Utilized Python, MATLAB, and Jupyter Notebook to pre-process signal datasets.
• Evaluated model performance against CNN, LSTM, and PCA architectures.

Designed and implemented a RISC-V branch prediction simulator in C++.

• Supported bimodal, gshare, and hybrid predictor architectures.
• Modeled dynamic two-bit counter tables and chooser logic.
• Optimized simulator runtime and validated against benchmark traces.

Developed a full-stack course management application using Ruby on Rails.

• Implemented core entities: Course, Enrollment, Feedback, Student, and Admin with secure authentication.
• Designed logic for waitlists, capacity tracking, and student enrollment history.
• Built feedback system allowing students to rate and comment on courses they completed.
• Enforced rigorous validations (e.g., non-negative capacity, email formats) and role-based access control.

Contributing to the complete architectural rewrite of the Expertiza peer-review platform.

• Migrating legacy Ruby on Rails MVC to a modern Rails API backend + React/TypeScript frontend.
• Reimplementing key controllers (e.g., Participants, Teams) to strictly follow RESTful principles and Single Responsibility.
• Developing new React front-end interfaces for Assignment creation and Student views.
• Ensuring code quality via RSpec testing and strict linting standards.

Backend refactoring and feature implementation for the production Expertiza system.

• Implemented a Grading Audit Trail to track grade changes and preserve instructor comments.
• Refactored complex controllers (e.g., ReviewMapping) to improve maintainability and performance.
• Enhanced the Authorization Helper to support JWT-based authentication for the new API.
• Optimized database queries to prevent N+1 issues in large-scale grading views.

A responsive web application to simplify splitting shared expenses among housemates.

• Dynamic UI: Add/Remove people and items dynamically with real-time total updates.
• Features: "Select All" functionality, tax distribution logic, and local PDF export using jsPDF.
• Tech Stack: Built with HTML5, Tailwind CSS, and Vanilla JavaScript for a lightweight, fast experience.
• UX: Includes an interactive guided tour to help new users understand the workflow.

A web-based tool for calculating and visualizing the Fast Fourier Transform (DIT-FFT) and Inverse FFT.

• Algorithm: Implements the Iterative Cooley-Tukey algorithm with bit-reversal permutation.
• Visualization: Displays stage-by-stage butterfly operation results for N=4, 8, and 16 points.
• Features: Complex number arithmetic class, dynamic table generation, and responsive dark-mode UI using Tailwind CSS.